Better circuits
in less time
ProMOST is a single-transistor dimensioning tool for analog and RF CMOS. Size and bias every device against your PDK's own compact model, in real time, one transistor at a time, so that your first full simulator run already starts near the optimum.
A 3N-dimensional,
non-linear problem
With the technology and the topology fixed, roughly three degrees of freedom remain per transistor: three quantities picked from {W, L, VGS, VGT, gm/ID, ID, gm}, with everything else following. A circuit with N transistors is therefore a 3N-dimensional optimization problem, and since transistors are non-linear, a non-linear one.
Three degrees of freedom, per device
Set {W, L, VGS} and ID and gm follow; set {L, VGT, gm} and W follows. VDS is usually not a degree of freedom at all, only a headroom minimum to satisfy.
No closed-form inverse
Modern compact models such as BSIM and PSP run to thousands of lines of code. You cannot invert them to get the W that meets your spec.
Tweak & simulate
Grab some initial sizes, fire up the simulator, examine the collective behaviour, tweak, re-run, tweak, re-run. Whether it converges depends entirely on the starting point.
Hand calculation, or
brute-force simulation
Designers today fall back on one of two extremes, and each one lacks what the other provides.
Back-of-the-envelope
- Fast, and full of insight
- Square-law models are inaccurate in modern CMOS
- Oversimplification quietly hides real artifacts
Brute-force optimizer / simulator
- Accurate: the full compact models
- Slow: huge search space, heavy CPU load, local minima
- No insight: you get numbers without understanding
Divide & conquer:
dimension per transistor
Instead of solving one enormous coupled problem, solve many small ones, each with the full, accurate model behind it.
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As it stands 45 dimensions
15 transistors × 3 degrees of freedom. Coarsely discretised: 345 ≈ 3·1021 combinations.
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Leverage symmetry 18 dimensions
Mirrors, cascodes and the differential pair collapse 15 transistors into 6 unique ones. The search space drops to 318 ≈ 4·108, a huge gain, and still far too hard.
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Optimize per transistor 6 × 3 dimensions
One hard 18-dimensional search becomes six easy 3-dimensional ones, solved consecutively. Low dimensionality means far less dependence on the initial guess. This is where ProMOST comes in, accurately and in real time.
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Then the simulator Near the optimum
Per-transistor optimization ignores interaction between devices, so the circuit ends up decently rather than fully optimized. The starting point is nonetheless as good as it can be, and that is what makes the circuit-level optimization fast.
It also tells you when the answer is "no". If the per-transistor step cannot dimension one or more devices for their targets, that is a conflict between requirements and design space, and it localizes the roadblock in the combination of {target specs, topology, technology}. Either the circuit relies on an interaction that was not captured per transistor, such as noise or distortion cancellation, or that topology in that technology simply cannot get there.
Be in charge. Enforce what each transistor must do, individually and collectively, instead of grabbing initial dimensions, running the simulator and reverse-engineering the result. Design your circuit; don't reverse-engineer your simulator. Read the full argument →
A real-time desktop
calculator for transistors
ProMOST is ChipDesignWorks' transistor sizing tool for CMOS technologies: a fast desktop calculator that lets designers determine optimum bias settings and device sizes per device, giving very fast circuit dimensioning, straightforward porting and clear bottleneck analysis.
- Calculate operating point information for specific bias settings, device sizes and temperature
- Calculate dimensions or bias conditions from a set of target performance metrics
- Perform constrained or unconstrained sweeps to find the optimum
- Calculate AC/RF properties: OIP, IIP, harmonic content, s-parameters and more
- Work directly in VGT, gm/ID or inversion level, the vocabulary of modern design methodologies
Fourfold speed advantage
ProMOST accelerates the design process at four separate stages.
Divide & conquer
Optimizing N transistors one by one is fundamentally faster than solving an MN-dimensional coupled non-linear problem all at once.
Near-optimum starting point
Using ProMOST for initial dimensioning means your first circuit-simulator run already starts close to the optimum, so iterations are fewer and shorter.
Simulator-accurate results
ProMOST runs the actual model in its own background solvers (op, dc, ac, noise), so results match your circuit simulator, with sub-second response.
Bottleneck identification
If a transistor cannot meet its budget, you know where your design is limited, and why.
Industrial designers
and research groups
Industrial IC designers
- Shorter design cycles: near-optimum first netlists and fewer simulator iterations.
- Systematic porting: re-solve every transistor's budgets in the new PDK. Same demands, new W, L and bias, so porting becomes a systematic exercise instead of an archaeological one.
- Bottleneck analysis for design reviews: defend every W and L with data.
- Fits your flow: stand-alone, inside your design suite, or scripted from Python and MATLAB.
PhD students & university groups
- Build real device intuition: explore any model parameter live, in the technology you actually tape out in.
- gm/ID and VGT methodologies map one-to-one onto the tool, including the inversion coefficient.
- Reproducible research: script every figure through TheRemote and export to XLS, CSV or TikZ.
- Teaching: the SquareLaw and simplified-EKV add-ins put the textbook model next to a real short-channel device.
New designs, and the
ones you already have
Starting from specs
Derive per-transistor budgets, dimension each device in seconds against the real model, then enter the simulator with a near-optimum design. What follows is a short, convergent loop.
Hours of structured dimensioning replace days of tweak-and-simulate, and you understand every choice you made.
Working on an existing circuit
Load a device's operating point and see immediately how far it sits from its optimum, and which spec it limits. Re-dimension only the critical devices at constant ID or gm, improving noise, linearity or speed without redesigning the circuit.
The same method ports a proven design to a new technology, device by device.
The reasoning,
in full
Four short documents work through the method and the device physics behind it, with examples taken straight out of ProMOST.
- Be in charge — why per-transistor dimensioning beats tweak-and-simulate, and what to do when the targets cannot be met.
- Models — element equations, transistor models, threshold-voltage definitions and layout-dependent stress effects.
- Small signal stuff — transcapacitances and transconductances, small-signal models and two worked circuits.
- Sweeps in ProMOST — basic sweeps, and constrained sweeps at constant ID or gm.
Your PDK's models,
on your platform
ProMOST supports many transistor models, including MOS11, PSP and the BSIM families, plus compound models: transistors extended with diodes, passives and juncaps, solved as one device with both per-component and equivalent operating-point data. It is used within major electronics companies, design houses and universities worldwide.
ProMOST runs on Linux and macOS, stand-alone or integrated in select IC design suites. It ships with add-ins for distortion, RF small-signal, switched configurations, W–L brute-force sweeps, bipolar devices and remote scripting.
News & releases
ProMOST is updated on average once a year with bug fixes, new features, added transistor models, and performance enhancements. A full update log is included with every software distribution package.